Publications-Full

Journal Publications

Appeared:

  1. B. Yin, J. R. Cavallaro, “LTE uplink MIMO receiver with low complexity interference cancellation,” Springer Analog Integrated Circuits and Signal Processing, DOI 10.1007/s10470-012-9945-1, pp. 443-450, Volume 73, Number 2, (November 2012, Published).
  2. M. Wu, C. Dick, Y. Sun, J. R. Cavallaro, “Low complexity scalable MIMO sphere detection through antenna detection reordering,” Springer Analog Integrated Circuits and Signal Processing, DOI 10.1007/s10470-012-9894-8, (July 2012, Online).
  3. Y. Sun, J. R. Cavallaro, “High-Throughput Soft-Output MIMO Detector Based on Path-Preserving Trellis-Search Algorithm,” IEEE Transactions on VLSI Systems, pp. 1235-1247, (July 2012).
  4. P. Radosavljevic, K. J. Kim, J. R. Cavallaro, “Parallel Searching based Sphere Detector for MIMO Downlink OFDM Systems,” IEEE Transactions on Signal Processing, DOI: 10.1109/TSP.2012.2190595, pp. 3240-3252, Volume 60, Number 6, (June 2012).
  5. Y. Sun, J. R. Cavallaro, “Trellis-Search Based Soft-Input Soft-Output MIMO Detector: Algorithm and VLSI Architecture,” IEEE Transactions on Signal Processing, DOI: 10.1109/TSP.2012.2187646, pp. 2617-2627, Volume 60, Number 5 (May 2012).
  6. M. Wu, Y. Sun, G. Wang, J. R. Cavallaro, “Implementation of a High Throughput 3GPP Turbo Decoder on GPU,” Springer Journal of Signal Processing Systems, Special Issue on SiPS 2010, DOI 10.1007/s11265-011-0617-7, (On-Line-First, 10 September 2011), pp. 171-183, Volume 65, Number 2, (November 2011).
  7. K. Amiri, M. Wu, J. R. Cavallaro, J. Lilleberg, “Cooperative Partial Detection Using MIMO Relays,” IEEE Transactions on Signal Processing, pp. 5039-5049, Volume 59, Number 10,(October 2011).
  8. Y. Sun, J. R. Cavallaro, “Efficient Hardware Implementation of a Highly-parallel 3GPP LTE/LTE-advance Turbo Decoder” Elsevier Integration, the VLSI Journal, Special Issue on Hardware Architectures for Algebra, Cryptology and Number Theory, DOI:10.1016/j.vlsi.2010.07.001, (On-Line, July 2010), pp. 305-315, Volume 44, Number 4, (September 2011).
  9. M. Wu, Y. Sun, S. Gupta, J. R. Cavallaro “Implementation of a High Throughput Soft MIMO Detector on GPU,” Springer Journal of Signal Processing Systems, pp.123-136, Volume 64, Number 1, (July 2011).
  10. Y. Sun, J. R. Cavallaro, “A Flexible LDPC/Turbo Decoder Architecture,” Springer Journal of Signal Processing Systems, Special Issue on the 2008 IEEE SiPS Workshop, DOI: 10.1007/s11265-010-0477-6,(On-Line First, April 2010), pp 1-16, Volume 64, Number 1, (July 2011).
  11. M. Myllylä, J. R. Cavallaro, M. Juntti, “Architecture Design and Implementation of the Metric First List Sphere Detector Algorithm,” IEEE Transactions on VLSI Systems, DOI: 10.1109/TVLSI.2010.2041800, pp. 895-899, Volume 19, Number 5, (May 2011).
  12. M. Myllylä, J. R. Cavallaro, M. Juntti, “Implementation Aspects of List Sphere Decoder Algorithms for MIMO-OFDM Systems,” Elsevier J. Signal Processing, (On-Line, April 2010), pp. 2863-2876,Volume 90, Number 10, (October 2010).
  13. J. Ketonen, M. Juntti, J. R. Cavallaro, “Performance – complexity Comparison of Receivers for a LTE MIMO–OFDM System,” IEEE Transactions on Signal Processing, pp. 3360-3372, Volume 58, Number 6, (June 2010).
  14. P. Radosavljevic, Y. Guo, J. R. Cavallaro, “Probabilistically Bounded Soft Sphere Detection for MIMO-OFDM Receivers: Algorithm and System Architecture,” IEEE Journal on Selected Areas in Communications, pp. 1318-1330, Volume 27, Number. 8, (October 2009).
  15. K. Amiri, J. R. Cavallaro, C. Dick, R. Rao, “A High Throughput Configurable SDR Detector for Multi-user MIMO Wireless Systems”, Springer Journal of Signal Processing Systems, Special Issue on Signal Processing for Software Defined Radio Handsets, (On-Line First, April 2009), pp. 233-245, Volume 62, Number 2, (February 2011).
  16. M. Karkooti, P. Radosavljevic, J. R. Cavallaro, “Configurable LDPC Decoder Architecture for Regular and Irregular Codes,” Springer Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, Special Issue: 20 Years of ASAP, pp. 73-88, Volume 53, (November 2008).
  17. V. Chandrasekhar, F. Livingston, J. R. Cavallaro, “Reducing Dynamic Power Consumption in Next Generation DS-CDMA Mobile Communication Receivers,” International Journal of Embedded Systems, pp. 128-140, Volume 3, Number 3, (2008).
  18. Y. Guo, J. Zhang, D. McCain, J. R. Cavallaro, “Structured Parallel Architecture for Displacement MIMO Kalman Equalizer in CDMA Systems,” IEEE Transactions on Circuits and Systems – II: Express Briefs, pp. 122-126, Volume 54, No. 2, (February 2007).
  19. Y. Guo, D. McCain, J. R. Cavallaro, A. Takach, “Rapid Industrial Prototyping and SoC Design of 3G/4G Wireless Systems Using a HLS Methodology,” EURASIP Journal on Embedded Systems, special issue on Signal Processing with High Complexity: Prototyping and Industrial Design, pp. 1-25, Volume 2006, Article ID 14952, DOI: 10.1155/ES/2006/14952, (2006).
  20. S. Rajagopal, J. R. Cavallaro, “Truncated On-line Arithmetic with Applications to Communication Systems,” IEEE Transactions on Computers, pp. 1240-1252, Volume 55, No. 10, (October 2006).
  21. Y. Guo, J. R. Cavallaro, “A Low Complexity and Low Power SoC Design Architecture for Adaptive MAI Suppression in CDMA Systems,” Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, pp. 195-217, Volume 44, No. 3, (September 2006).
  22. Y. Guo, J. Zhang, D. McCain, J. R. Cavallaro, “An Efficient Circulant MIMO Equalizer for CDMA Downlink: Algorithm and VLSI Architecture,” EURASIP Journal on Applied Signal Processing, Special Issue on Implementation Aspects and Testbeds for MIMO Systems, Volume 2006, Article ID 57134, 18 pages, DOI:10.1155/ASP/2006/57134, (2006).
  23. S. Das, E. Erkip, J. R. Cavallaro, B. Aazhang, “Low Complexity Iterative Multiuser Detection and Decoding for Real-Time Applications,” IEEE Transactions on Wireless Communications, pp. 1455-1460, Volume 4, No. 4, (July 2005).
  24. M. L. Leuschen, I. D. Walker, J. R. Cavallaro, “Fault Residual Generation via Nonlinear Analytical Redundancy,” IEEE Transactions on Control Systems Technology, pp. 452-458, Volume 13, No. 3, (May 2005).
  25. S. Rajagopal, J. R. Cavallaro, S. Rixner, “Design Space Exploration for Real-Time Embedded Stream Processors,” IEEE Micro, pp. 54-66, Volume 24, No. 4, (July-August 2004).
  26. B. Jones, J. R. Cavallaro, “A Rapid Prototyping Environment for Wireless Communication Embedded Systems,” EURASIP Journal on Applied Signal Processing, Special Issue on: Rapid Prototyping of DSP Systems, pp. 603-614, Volume 2003, No. 6, (May 2003).
  27. J. R. Cavallaro, “Architectures for Heterogeneous Multi-Tier Networks,” Kluwer Journal on Wireless Personal Communications, pp. 285-296, Volume 22, No. 2, (August 2002).
  28. S. Rajagopal, S. Bhashyam, J. R. Cavallaro, B. Aazhang, “Real-Time Algorithms and Architectures for Multiuser Channel Estimation and Detection in Wireless Base-Station Receivers,” IEEE Transactions on Wireless Communications, pp. 468-479, Volume 1, No. 3, (July 2002).
  29. S. Rajagopal, S. Bhashyam, J.R. Cavallaro, B. Aazhang, “Efficient VLSI Architectures for Multiuser Channel Estimation in Wireless Base-station Receivers”, Journal of VLSI Signal Processing: special issue on ASAP, pp. 143-156, Volume 31, No. 2, (June 2002).
  30. G. Xu, S. Rajagopal, J. R. Cavallaro, B. Aazhang, “VLSI Implementation of the Multistage Detector for Next Generation Wideband CDMA Receivers”, Journal of VLSI Signal Processing: special issue on signal processing for wireless communications: algorithms, performance and architecture, pp. 21-33, Volume 30, No. 1-3, (March 2002).
  31. B. Aazhang, J. R. Cavallaro, “Multi-tier Wireless Communications,” Wireless Personal Communications, Special Issue on Future Strategy for the New Millennium Wireless World, Kluwer, pp. 323-330, Volume 17, (June 2001).
  32. C. Sengupta, J. R. Cavallaro, B. Aazhang, “On Multipath Channel Estimation for CDMA Systems Using Multiple Sensors,” IEEE Transactions on Communications, pp. 543-553, Volume 49, No. 3, (March 2001).
  33. M. L. Leuschen, I. D. Walker, J. R. Cavallaro, “Evaluating the Reliability of Prototype Degradable Systems,” Reliability Engineering and System Safety, pp. 9-20, Volume 72, (2001).
  34. C. Sengupta, J. R. Cavallaro, B. Aazhang, “Subspace-based Tracking of Multipath Channel Parameters for CDMA Systems,” European Transactions on Telecommunications, pp. 439-447, Volume 9, No. 5, (September – October 1998).
  35. J. Feinsmith, J. H. Aylor, R. Hodson, B. Courtois, J. R. Cavallaro, J. Hines, C. Pina, M. Smith, D. Bouldin, “What’s Next for Microelectronics Education – Editorial” IEEE Design and Test of Computers, pp. 95-102, Volume 14, No. 4, (October-December 1997).
  36. C. Sengupta, J. R. Cavallaro, W. L. Wilson, Jr., F. K. Tittel, “Automated Evaluation of Critical Features in VLSI Layouts Based on Photolithographic Simulations,” IEEE Transactions on Semiconductor Manufacturing, pp. 482-494, Volume 10, No. 4, (1997).
  37. Z. L. Horvath, M. Erdélyi, G. Szabó, Zs. Bor, F. K. Tittel, J. R. Cavallaro, “Generation of Nearly Nondiffracting Bessel Beams with a Fabry-Perot Interferometer,” Journal of the Optical Society of America A, pp. 3009-3013, Volume 14, No. 11, (November 1997).
  38. M. Erdélyi, Z. L. Horvath, G. Szabó, Zs. Bor, F. K. Tittel, J. R. Cavallaro, M. C. Smayling, “Generation of Diffraction-free Beams for Applications in Optical Microlithography,” Journal of Vacuum Science and Technology B, pp. 287-292, Volume 15, No. 2, (March/April 1997).
  39. K. E. Petersen, I. D. Walker, J. R. Cavallaro, “Safety of Robotic Systems – Guest Editorial,” Reliability Engineering and System Safety, pp. 223-224, Volume 53, No. 3, (1996).
  40. D. Walker, J. R. Cavallaro, “Failure Mode Analysis for a Hazardous Waste Clean-up Manipulator,” Reliability Engineering and System Safety, pp. 277-290, Volume 53, No. 3, (1996).
  41. M. Erdélyi, Zs. Bor, J. R. Cavallaro, G. Szabó, W. L. Wilson, Jr., C. Sengupta, M. C. Smayling, F. K. Tittel, “Enhanced Microlithography Using Combined Phase Shifting and Off-Axis Illumination,” Japanese Journal of Applied Physics, pp. L1629-L1631, Volume 34, Part 2, No. 12A, (December 1995).
  42. M. Kido, G. Szabó, J. R. Cavallaro, W. L. Wilson, Jr., M. C. Smayling, F. K. Tittel, “Submicron Optical Lithography Based on a New Interferometric Phase Shifting Technique,” Japanese Journal of Applied Physics, pp. 4269-4273, Volume 34, Part 1, No. 8A, (August 1995).
  43. M. L. Visinsky, J. R. Cavallaro, I. D. Walker, “A Dynamic Fault Tolerance Framework for Remote Robots,” IEEE Transactions on Robotics and Automation, pp. 477-490, Volume 11, No. 4, (1995).
  44. M. L. Visinsky, J. R. Cavallaro, I. D. Walker, “Robotic Fault Detection and Fault Tolerance: A Survey,” Reliability Engineering and System Safety, pp. 139-158, Volume 46, No. 2, (1994).
  45. N. D. Hemkumar, J. R. Cavallaro, “Redundant and On-Line CORDIC for Unitary Transformations,” IEEE Transactions on Computers, Special Issue on Computer Arithmetic, pp. 941-954, Volume 43, No. 8, (August 1994).
  46. M. L. Visinsky, J. R. Cavallaro, I. D. Walker, “Expert System Framework for Fault Detection and Fault Tolerance in Robotics,” Computers and Electrical Engineering, pp. 421-435, Volume 20, No. 5, (1994).
  47. I.D. Walker, J. R. Cavallaro, “Parallel VLSI Architectures for Real-Time Kinematics of Redundant Robots,” Journal of Intelligent and Robotic Systems: Theory and Applications, Special Issue on Computational Aspects of Robot Kinematics, pp. 25-43, Volume 9, No. 1, (1994).
  48. N. D. Hemkumar, J. R. Cavallaro, “Simulation of Systolic Arrays on the Connection Machine,” SCS Simulation, Special Issue on High Performance Computing, pp. 151-159, Volume 61, No. 3, (September 1993).
  49. K. Kota, J. R. Cavallaro, “Numerical Accuracy and Hardware Tradeoffs for CORDIC Arithmetic for Special-Purpose Processors,” IEEE Transactions on Computers, pp. 769-779, Volume 42, No. 7, (July 1993).
  50. J. R. Cavallaro, F. T. Luk, “CORDIC Arithmetic for an SVD Processor,” Journal of Parallel and Distributed Computing, pp. 271-290, Volume 5, No. 3, (June 1988).

Contributions to Books

  1. Y. Sun, K. Amiri, G. Wang, B. Yin, J. R. Cavallaro, T. Ly, “High-Level Design Tools for Complex DSP Applications,” (R. Oshana, M. Brogioli, Eds.), Elsevier Digital Signal Processing Handbook, Elsevier, Waltham, MA, pp. 133-155, (2012).
  2. K. Amiri, M. Duarte, J. R. Cavallaro, C. Dick, R. Rao, A. Sabharwal, “FPGA in Wireless Communications Applications,” (R. Oshana, M. Brogioli, Eds.), Elsevier Digital Signal Processing Handbook, Elsevier, Waltham, MA, pp. 75-101, (2012).
  3. Y. Sun, K. Amiri, P. Radosavljevic, J. R. Cavallaro, “Application-Specific DSP Accelerators,” (S. Bhattacharyya, E. Deprettere, R. Leupers, J. Takala, Eds.), in Springer Handbook on Signal Processing Systems, 1st Edition, Springer, New York, NY, pp. 329-362, (2010).
  4. Y. Sun, J. R. Cavallaro, Y. Zhu, M. Goel, “Configurable and Scalable Turbo Decoder Architecture for Multiple 4G Wireless Standards” (S. Adibi, A. Mobasher, T. Tofigh, Eds.) in Fourth-Generation (4G) Wireless Networks: Applications and Innovations, IGI-Global Press, pp. 622-643, (2010).
  5. S. Rajagopal, J. R. Cavallaro, “Communication Processors,” (B. W. Wah, Ed.), in Wiley Encyclopedia of Computer Science and Engineering, pp. 471-482, (2009).
  6. M. L. Leuschen, I. D. Walker, J. R. Cavallaro “Nonlinear Fault Detection for Hydraulic Systems,” Fault Diagnosis and Fault Tolerance for Mechatronic Systems, Recent Advances, (F. Caccavale and Luigi Villani, Eds.), (Springer Tracts in Advanced Robotics Volume I, (B. Siciliano, O. Khatib, and F. Groen, Series Eds.), Springer-Verlag, Berlin Heidelberg, Germany, pp. 169-191, (2003).
  7. M. L. Visinsky, J. R. Cavallaro, I. D. Walker, “Chapter 3: Robotic Fault Tolerance: Algorithms and Architectures,” Robotics and Remote Systems in Hazardous Environments, (M. Jamshidi and P. J. Eicker, Eds.), Prentice Hall, Englewood Cliffs, NJ, pp. 53-73, (1993).

Conference Publications

  1. G. Wang, Y. Xiong, J. Yun, and J. R. Cavallaro, “Accelerating Computer Vision Algorithms Using Opencl Framework on Mobile Devices – A Case Study,” 2013 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), May 26-31, 2013, Vancouver, Canada (December 2012, Submitted).
  2. B. Yin, M. Wu, C. Studer, J. R. Cavallaro, and C. Dick, “Implementation Trade-Offs For Linear Detection In Large-Scale Mimo Systems,” 2013 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), May 26-31, 2013, Vancouver, Canada (December 2012, Submitted).
  3. B. Rister, G. Wang, M. Wu and J. R. Cavallaro, “A Fast and Efficient Sift Detector Using The Mobile Gpu,” 2013 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), May 26-31, 2013, Vancouver, Canada (December 2012, Submitted).
  4. G. Wang, A. Vosoughi, H. Shen, J. R. Cavallaro and Y. Guo, “Parallel Interleaver Architecture with New Scheduling Scheme for High Throughput Configurable Turbo Decoder,” IEEE International Symposium on Circuits and Systems (ISCAS 2013), Beijing, China, May 2013 (October 2012, Submitted, December 2012, Accepted).
  5. M. Wu, B. Yin, A. Vosoughi, C. Studer, J. R. Cavallaro and C. Dick, “Approximate Matrix Inversion for High-Throughput Data Detection in Large-Scale MIMO Uplink, “ IEEE International Symposium on Circuits and Systems (ISCAS 2013), Beijing, China, May 2013 (October 2012, Submitted, December 2012, Accepted).
  6. S. Su, J. Kerwin, S. Crowe, J. R. Cavallaro and G. L. Woods, “Teaching Embedded Programming to Electrical Engineers, BioEngineers, and Mechanical Engineers via the Escape Platform,” 3rd Interdisciplinary Engineering Design Education Conference (IEDEC 2013), Santa Clara, CA, March 2013, ( October 2012, Submitted, December 2012, Accepted ).
  7. S. C. Kim, W. L. Plishker, S. S. Bhattacharyya and Joseph R. Cavallaro, “GPU-Based Acceleration of Symbol Timing Recovery,” Conference on Design & Architectures for Signal & Image Processing (DASIP 2012), Karlsruhe, Germany, (October 2012) (Accepted, June 2012, Published, December 2012 ).
  8. J. Ketonen, M. Juntti, J. Ylioinas, and J. R. Cavallaro, “Implementation of LS, MMSE and SAGE Channel Estimators for Mobile MIMO-OFDM,” 2012 IEEE Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, (November 2012) (Submitted, May 2012, Accepted, June 2012, Published, December 2012).
  9. G. Wang, H. Shen, B. Yin, Y. Sun, and J. R. Cavallaro, “Parallel Nonbinary LDPC Decoding on GPU,,” 2012 IEEE Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, (November 2012) (Submitted, May 2012, Accepted, June 2012, Published, December 2012).
  10. B. Yin, M. Wu, G. Wang and J. R. Cavallaro, “Low Complexity Opportunistic Decoder for Network Coding,” 2012 IEEE Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, (November 2012) (Submitted, May 2012, Accepted, June 2012, Published, December 2012).
  11. A. Vosoughi, M. Wu, and J. R. Cavallaro, “Baseband Signal Compression in Wireless Base Stations,” IEEE Global Communications Conference (GLOBECOM), Anaheim, CA, (December 2012) (Submitted, March 2012, Accepted, July 2012).
  12. M. Wu, B. Yin, and J. R. Cavallaro, “Flexible N-Way MIMO Detector on GPU,” IEEE Workshop on Signal Processing Systems (SiPS 2012), pp. 318-323,Québec City, Québec, Canada, (October 2012) (Accepted June 2012).
  13. S. C. Kim, W. L. Plishker, S. S. Bhattacharyya and Joseph R. Cavallaro, “Gpu-Based Acceleration of Symbol Timing Recovery,” Conference on Design & Architectures for Signal & Image Processing (DASIP 2012), Karlsruhe, Germany, (October 2012) (Accepted June 2012).
  14. B. Yin, K. Amiri, J. R. Cavallaro, and Y. Guo, “Reconfigurable Multi-Standard Uplink MIMO Receiver with Partial Interference Cancellation,” IEEE International Conference on Communications (ICC), pp. 6282-6286, Ottawa, Canada, (Submitted, September 2011, Accepted, January 2012), (June 2012).
  15. M. Wu, C. Dick, J. R. Cavallaro, “Improving MIMO Sphere Detection Through Antenna Detection Order Scheduling,” Software Defined Radio Forum 2011, pp. 280-284, Washington, DC, (November-December 2011), (Accepted, August 2011) (June 2012).
  16. B. Yin, J. R. Cavallaro, “Low complexity MMSE based interference cancellation for LTE uplink MIMO receiver,” Software Defined Radio Forum 2011, pp. 18-22, Washington, DC, (November-December 2011), (Accepted, August 2011) (June 2012)
  17. G. Wang, M. Wu, Y. Sun, J. R. Cavallaro, “GPU Accelerated Scalable Parallel Decoding of LDPC Codes,” 2011 IEEE Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, pp. 2053-2057, (November 2011), (Submitted, May 2011, Accepted, July 2011, Published, March 2012).
  18. G. Wang, M. Wu, Y. Sun, J. R. Cavallaro, “High-Throughput Contention-Free Concurrent Interleaver Architecture for Multi-Standard Turbo Decoder,” IEEE International Conference on Application-specific System, Architectures and Processors (ASAP’11), pp. 113-121, Santa Monica, CA (Accepted, June 2011),(September 2011)
  19. G. Wang, M. Wu, Y. Sun, J. R. Cavallaro, “A Massively Parallel Implementation of QC-LDPC Decoder on GPU,” IEEE Symposium on Application Specific Processors (SASP), pp. 82-85, San Diego, CA, (June 2011).
  20. Y. Sun, G. Wang, and J. R. Cavallaro, “Multi-Layer Parallel Decoding Algorithm and VLSI Architecture for Quasi-Cyclic LDPC Codes,” IEEE ISCAS Special Session on VLSI Architectures for LDPC coding/decoding, pp. 1776-1779, Rio de Janeiro, Brazil, (May 2011).
  21. K. Amiri, C. Dick, R. Rao, J. R. Cavallaro, “Reduced Complexity Soft MMSE MIMO Detector Architecture,” Software Defined Radio Forum 2010, (Outstanding Paper Award), pp. 716-720, Washington, DC, (November-December 2010).
  22. M. Wu, Y. Sun, J. R. Cavallaro, “Implementation of a 3GPP LTE Turbo Decoder Accelerator on GPU,” IEEE Workshop on Signal Processing Systems (SiPS), pp. 192-197, San Francisco, CA, (October 2010).
  23. O. Gustafsson, K. Amiri, D. Andersson, A. Blad, C. Bonnet, J. R. Cavallaro, J. Declerck, A. Dejonghe, P. Eliardsson, M. Glasse, A. Hayar, L. Hollevoet, C. Hunter, M. Joshi, F. Kaltenberger, R. Knopp, K. Le, Z. Miljanic, P. Murphy, F. Naessens, N. Nikaein, D. Nussbaum, R. Pacalet, P. Raghavan, A. Sabharwal, O. Sarode, P. Spasojevic, Y. Sun, H. M. Tullberg, T. Vander Aa, L. Van der Perre, M. Wetterwald, and M. Wu, “Architectures for Cognitive Radio Testbeds and Demonstrators – An Overview,” Invited Special Session, 2010 5th International Conference on Cognitive Radio Oriented Wireless Networks and Communications (CROWNCOM), Cannes, France, (June 2010).
  24. K. Amiri, M. Wu, M. Duarte, J. R. Cavallaro, “Physical Layer Algorithm and Hardware Verification of MIMO Relays Using Cooperative Partial Detection,” IEEE ICASSP, pp. 5614-5617, Dallas, TX, (March 2010).
  25. Y. Sun, J. R. Cavallaro, “Low-Complexity and High-Performance Soft MIMO Detection Based on Distributed M-Algorithm through Trellis-Diagram,” IEEE ICASSP, pp. 3398-3401, Dallas, TX, (March 2010).
  26. M. C. Brogioli, J. R Cavallaro, “Compiler Driven Architecture Design Space Exploration for Embedded DSP Workloads: A Study in Software Programmability Versus Hardware Acceleration,” 2009 IEEE Asilomar Conference on Signals, Systems, and Computers, pp. 221-225, Pacific Grove, CA, (November 2009).
  27. G. Wang, B. Yin, K. Amiri, Y. Sun, J. R. Cavallaro, “FPGA Prototyping of a High Data Rate LTE Uplink Baseband Receiver,” 2009 IEEE Asilomar Conference on Signals, Systems, and Computers, pp. 248-252, Pacific Grove, CA, (November 2009)
  28. M. Wu, Y. Sun, J. R. Cavallaro, “Reconfigurable Real-time MIMO Detector on GPU,” 2009 IEEE Asilomar Conference on Signals, Systems, and Computers, pp. 690-694, Pacific Grove, CA, (November 2009).
  29. J. Ketonen, M. Juntti, J. R. Cavallaro, “Receiver Implementation for MIMO-OFDM with AMC and Precoding,” 2009 IEEE Asilomar Conference on Signals, Systems, and Computers, pp. 1268-1272, Pacific Grove, CA, (November 2009).
  30. M. Wu, S. Gupta, Y. Sun, J. R. Cavallaro, “A GPU Implementation of a Real-Time MIMO Detector,” IEEE Workshop on Signal Processing Systems (SiPS), pp. 303-308, Tampere, Finland, (October 2009).
  31. Y. Sun, J. R. Cavallaro, T. Ly, “Scalable and Low Power LDPC Decoder Design Using High Level Algorithmic Synthesis,” 22nd IEEE International SOC Conference, pp. 267-270, Belfast, Northern Ireland, (September 2009).
  32. Y. Sun, J. R. Cavallaro, “High Throughput VLSI Architecture for Soft-Output MIMO Detection Based on a Greedy Graph Algorithm”, ACM/IEEE Great Lakes Symposium on VLSI, (Best Student Paper Award), pp. 445-450, Boston, MA, (May 2009).
  33. M. Myllylä, M. Juntti, J. R. Cavallaro “Architecture Design and Implementation of the Increasing Radius – List Sphere Detector Algorithm,” IEEE ICASSP, pp. 553.556, Taipei, Taiwan, (April 2009).
  34. K. Amiri, J. R. Cavallaro, “Partial Detection for Multiple Antenna Cooperation”, CISS, pp. 669-674, Baltimore, MD, (March 2009).
  35. K. Amiri, C. Dick, R. Rao, J. R. Cavallaro, “Novel Sort-Free Detector with Modified Real-valued Decomposition Ordering in MIMO Systems,” IEEE Global Communications Conference (GLOBECOM), pp. 1-5, New Orleans, LA, (Nov.-Dec. 2008).
  36. P. Radosavljevic, K. J. Kim, J. R. Cavallaro, “QRD-QLD searching based sphere detection for emerging MIMO downlink OFDM receivers”, IEEE Global Communications Conference (GLOBECOM), pp. 1-5,New Orleans, LA,(Nov.-Dec. 2008).
  37. K. Amiri, C. Dick, R. Rao, J. R. Cavallaro, “Flex-Sphere: An FPGA Configurable Sort-Free Sphere Detector for Multi-user MIMO Wireless Systems,” Software Defined Radio Forum 2008, Washington, DC, (October 2008).
  38. C. Dick, K. Amiri, J. R. Cavallaro, R. Rao, “Design and Architecture of Spatial Multiplexing MIMO Decoders for FPGAs”, Invited Paper, 2008 IEEE Asilomar Conference on Signals, Systems, and Computers, pp. 160-164, Pacific Grove, CA, (October 2008).
  39. Y. Sun, J. R. Cavallaro, “Unified Decoder Architecture for LDPC/Turbo Codes,” 2008 IEEE Workshop on Signal Processing Systems, (SiPS), pp. 13-18, Washington, DC, (Awarded “Bob Owens Memorial Paper Award.”), (October 2008).
  40. M. Myllylä, M. Juntti, J. R. Cavallaro, “Implementation and Complexity Analysis of List Sphere Detector for MIMO-OFDM Systems,” 2008 IEEE Asilomar Conference on Signals, Systems, and Computers, pp. 1852-1856, Pacific Grove, CA, (October 2008).
  41. J. Ketonen, M. Myllylä, M. Juntti, J. R. Cavallaro, “ASIC Implementation Comparison of SIC and LSD Receivers for MIMO-OFDM,” 2008 IEEE Asilomar Conference on Signals, Systems, and Computers, pp. 1881-1885, Pacific Grove, CA, (October 2008).
  42. Y. Sun, J. R. Cavallaro, “A New MIMO Detector Architecture Based on a Forward-Backward Trellis Algorithm,” 2008 IEEE Asilomar Conference on Signals, Systems, and Computers, pp. 1892-1896, Pacific Grove, CA, (October 2008).
  43. Y. Sun, J. R. Cavallaro, “A Low Power 1-Gbps Reconfigurable LDPC Decoder Design for Multiple 4G Wireless Standards,” IEEE International SoC Conference (SOCC’08), pp. 367-370, Newport Beach, CA, (Best Paper Award), (September 2008).
  44. M. Myllylä, M. Juntti, J. R. Cavallaro, “The Effect of Preprocessing to the Complexity of List Sphere Detector Algorithms,” 2008 WPMC, Lapland, Finland, (September 2008).
  45. Y. Sun, Y. Zhu, M. Goel, J. R. Cavallaro, “Configurable and Scalable High Throughput Turbo Decoder Architecture for Multiple 4G Wireless Standards,” IEEE International Conference on Application-specific System, Architectures and Processors (ASAP’08), pp. 209-214, Leuven, Belgium (July 2008).
  46. M. Karkooti, J. R. Cavallaro, “Distributed Decoding in Cooperative Communications,“ 2007 IEEE Asilomar Conference on Signals, Systems, and Computers, pp. 824-828, Pacific Grove, CA, (November 2007).
  47. M. Myllylä, J. Antikainen, M. Juntti, J. R. Cavallaro, “The Effect of LLR Clipping to the Complexity of List Sphere Detector Algorithms,” 2007 IEEE Asilomar Conference on Signals, Systems, and Computers, pp. 1559-1563, Pacific Grove, CA, (November 2007).
  48. Y. Guo, J. R. Cavallaro, “Scalable Architecture of MIMO Multi-carrier CDMA System on Programmable Logic,” 2007 IEEE Asilomar Conference on Signals, Systems, and Computers, pp. 1976-1980, Pacific Grove, CA, (November 2007).
  49. K. Amiri, P. Radosavljevic, J. R. Cavallaro, “Architecture and Algorithm for a Stochastic Soft-output MIMO Detector,” 2007 IEEE Asilomar Conference on Signals, Systems, and Computers, pp. 1034-1038, Pacific Grove, CA, (November 2007).
  50. M. Gadhiok, J. R. Cavallaro, “Preamble-based Symbol Timing Estimation for Wireless OFDM Systems,” 2007 IEEE Asilomar Conference on Signals, Systems, and Computers, pp. 1791-1794, Pacific Grove, CA, (November 2007).
  51. K. Amiri, Y. Sun, P. Murphy, C. Hunter, J. R. Cavallaro, A. Sabharwal, “WARP, a Unified Wireless Network Testbed for Education and Research,” IEEE International Conference on Microelectronic Systems Education (MSE), pp. 53-54, San Diego, CA, (June 2007).
  52. Y. Sun, M. Karkooti, J. R. Cavallaro, “VLSI Decoder Architecture for High Throughput,Variable Block-size and Multi-rate LDPC Codes,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2104-2107, New Orleans, LA, (May 2007).
  53. K. Amiri, Y. Sun, P. Murphy, C. Hunter, J. Cavallaro, A. Sabharwal, “WARP, a Modular Testbed for Configurable Wireless Network Research at Rice,” IEEE Galveston Bay Section Symposium for Space Applications of Wireless and RFID 2007, (March 2007).
  54. M. Myllylä, M. Juntti, M. Limingoja, A. Byman, J. R. Cavallaro, “Performance Evaluation of Two LMMSE Detectors in a MIMO-OFDM Testbed,” Proc. IEEE 40th Asilomar Conference on Signals, Systems, and Computers, pp. 1161-1165, Pacific Grove, CA, (October-November 2006).
  55. M. Brogioli, P. Radosavljevic, J. Cavallaro, “A General Hardware/Software Codesign Methodology For Embedded Signal Processing and Multimedia Workloads,” Proc. IEEE 40th Asilomar Conference on Signals, Systems, and Computers, pp. 1486-1490, Pacific Grove, CA, (October-November 2006).
  56. K. Amiri, J. R. Cavallaro, “FPGA Implementation of Dynamic Threshold Sphere Detection for MIMO Systems,” Proc. IEEE 40th Asilomar Conference on Signals, Systems, and Computers, pp. 94-98, Pacific Grove, CA, (October-November 2006).
  57. P. Radosavljevic, J. R. Cavallaro, “Soft Sphere Detection with Bounded Search for High-Throughput MIMO Receivers,” Proc. IEEE 40th Asilomar Conference on Signals, Systems, and Computers, pp. 1175-1179, Pacific Grove, CA, (October-November 2006).
  58. Y. Sun, M. Karkooti, J. R. Cavallaro, “High Throughput, Parallel, Scalable LDPC Encoder/Decoder Architecture for OFDM Systems,” Proc. 5th IEEE Dallas Circuits and Systems Workshop on Design, Applications, Integration and Software, pp. 39-42, Dallas, TX, (October 2006).
  59. M. Karkooti, P. Radosavljevic, J. R. Cavallaro, “Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation,” Proc. IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp. 360-367, Steamboat Springs, CO (September 2006).
  60. P. Radosavljevic, M. Karkooti, A. deBaynast, J. R. Cavallaro, “High-Throughput Multi-Rate LDPC Decoder Based On Architecture-Oriented Parity Check Matrices,” 14th European Signal Processing Conference, Firenze, Italy, (September 2006).
  61. P. Radosavljevic, A. de Baynast, M. Karkooti, J. R. Cavallaro, “Multi-Rate High-Throughput LDPC Decoder: Tradeoff Analysis Between Decoding Throughput and Area,” Proc. 17th Annual IEEE International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC’06), DOI: 10.1109/PIMRC.2006.254392, Helsinki, Finland, (September 2006).
  62. M. Myllylä, P. Silvola, M. Juntti, J. R. Cavallaro, “Comparison of Two Novel List Sphere Detector Algorithms For MIMO-OFDM Systems,” Proc. 17th Annual IEEE International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC’06), DOI: 10.1109/PIMRC.2006.254384, Helsinki, Finland, (September 2006).
  63. M. Brogioli, P. Radosavljevic, J. R. Cavallaro, “Hardware/Software Co-design Methodology for DSP/FPGA Partitioning: A Case Study for Meeting Real-Time Processing Deadlines in 3.5G Mobile Receivers,” Proc. 49th IEEE International Midwest Symposium on Circuits and Systems, San Juan, PR, (August 2006).
  64. M. Brogioli, M. Gadhiok, J. R. Cavallaro, “Design and Analysis of Heterogeneous DSP/FPGA Based Architectures for 3GPP Wireless Systems,” IEEE Real-Time and Embedded Technology and Applications Symposium; Work-in-Progress Sessions, pp. 29-32, San Jose, CA, (April 2006).
  65. P. Radosavljevic, A. deBaynast, J. R. Cavallaro, “Optimized Message Passing Schedules for LDPC Decoding,” Proc. IEEE 39th Asilomar Conference on Signals, Systems, and Computers, pp. 591-595, Pacific Grove, CA, (October-November 2005).
  66. M. Karkooti, J. R. Cavallaro, C. Dick, “FPGA Implementation of Matrix Inversion Using QRD-RLS Algorithm,” Proc. IEEE 39th Asilomar Conference on Signals, Systems, and Computers, pp. 1625-1629, Pacific Grove, CA, (October-November 2005).
  67. M. Myllylä, J.-M. Hintikka, J. R. Cavallaro, M. Juntti, M. Limingoja, A. Byman, “Complexity Analysis of MMSE Detector Architectures for MIMO OFDM Systems,” Proc. IEEE 39th Asilomar Conference on Signals, Systems, and Computers, pp. 75-81, Pacific Grove, CA, (October-November 2005).
  68. M. Brogioli, J. R. Cavallaro, “Modelling Heterogeneous DSP–FPGA Based System Partitioning with Extensions to the Spinach Simulation Environment,” Proc. IEEE 39th Asilomar Conference on Signals, Systems, and Computers, pp. 1630-1634, Pacific Grove, CA, (October-November 2005).
  69. Y. Guo, J. Zhang, D. McCain, J. R. Cavallaro, “Displacement MIMO Kalman Equalizer for CDMA Downlink in Fast Fading Channels,” Proc. IEEE GLOBECOM, pp. 2281-2286, St. Louis, MO, (November 2005).
  70. Y. Guo, D. McCain, J. R. Cavallaro, “Hermitian Optimization and Scalable VLSI Architecture for Circulant Approximated MIMO Equalizer in CDMA Downlink,” Proc. IEEE Vehicular Technology Conference (VTC), pp. 2096-2101, Dallas, TX, (September 2005).
  71. Y. Guo, D. McCain, J. R. Cavallaro, “Low Power VLSI Architecture for Adaptive MAI Suppression in CDMA Using Multi-stage Convergence Masking Vector,” Proc. IEEE Vehicular Technology Conference (VTC), pp. 1761-1766, Dallas, TX, (September 2005).
  72. J. R. Cavallaro, “VLSI Architectures and Rapid Prototyping Testbeds for Wireless Systems,” International Workshop on Convergent Technologies (IWCT), Oulu, Finland, (June 2005).
  73. M. Gadhiok, R. Hardy, P. Murphy, P. Frantz, H. Choi, J. R. Cavallaro, “An FPGA-based Daughtercard for TI’s C6000 family of DSKs,” Proc. IEEE International Conference on Microelectronic Systems Education (MSE), pp. 85-86, Anaheim, CA, (June 2005).
  74. Y. Guo, D. McCain, J. R. Cavallaro, “FFT-Accelerated Iterative MIMO Chip Equalizer Architecture for CDMA Downlink,” IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), Volume 3, pp. 1005-1008, Philadelphia, PA (March 2005).
  75. J. R. Cavallaro, M. C. Brogioli, A. de Baynast, P. Radosavljevic, “Reconfigurable Architectures for Wireless Systems: Design Exploration and Integration Challenge,” Wireless World Research Forum (WWRF-12), Toronto, Canada (November 2004).
  76. S. Rajagopal, S. Rixner, J. R. Cavallaro, “Improving Power Efficiency in Stream Processors Through Dynamic Cluster Reconfiguration,” 6th Workshop on Media and Streaming Processors, Portland, OR, (December 2004).
  77. Y. Guo, J. Zhang, D. McCain, J. R. Cavallaro, “Efficient MIMO Equalization for Downlink Multi-Code CDMA: Complexity Optimization and Comparative Study,” Proc. IEEE GLOBECOM, Volume 4, pp. 2513 – 2519, Dallas, TX, (November 2004).
  78. A. de Baynast, P. Radosavljevic, J. R. Cavallaro, “Chip level LMMSE Equalization for Downlink MIMO CDMA in Fast Fading Environments,” Proc. IEEE GLOBECOM, Volume 4, pp. 2552-2556, Dallas, TX, (November 2004).
  79. P. Radosavljevic, J. Cavallaro, A. de Baynast, “ASIP Architecture Implementation of Channel Equalization Algorithms for MIMO Systems in WCDMA Downlink,” Proc. IEEE 60th Vehicular Technology Conference (VTC2004-Fall), Volume 3, pp. 1735-1739, Los Angeles, CA (September 2004).
  80. J. R. Cavallaro, P. Radosavljevic, “ASIP Architecture for Future Wireless Systems: Flexibility and Customization,” Wireless World Research Forum (WWRF-11), Oslo, Norway (June 2004).
  81. Y. Guo, D. McCain, J. R. Cavallaro, “Low Complexity System-On-Chip Architectures of Optimal Parallel-Residue-Compensation In CDMA Systems,” Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 77-80, Volume 4, Vancouver, Canada (May 2004).
  82. M. Karkooti, J. Cavallaro, “Semi-parallel Reconfigurable Architectures for Real-time LDPC Decoding,” Proc. IEEE International Conference on Information Technology (ITCC), pp. 579-585, Volume 1, Las Vegas, NV (April 2004).
  83. Y. Guo, D. McCain, J. Zhang J. R. Cavallaro, “Scalable FPGA Architectures for LMMSE-based SIMO Chip Equalizer in HSDPA Downlink,” Proc. 37th Asilomar Conference on Signals, Systems, and Computers, Volume 2, pp. 2171 – 2175, Pacific Grove, CA, (November 2003).
  84. V. Chandrasekhar, F. Livingston, J. R. Cavallaro, “Reducing Dynamic Power Consumption in Next Generation DS-CDMA Mobile Communication Receivers,” Proc. IEEE 14th International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp. 251-261, The Hague, The Netherlands (June 2003).
  85. Y. Guo, G. Xu, D. McCain, J. R. Cavallaro, “Rapid Scheduling of Efficient FPGA Architectures for Next-Generation HSDPA Wireless System Using Precision C Synthesizer,” Proc. 14th IEEE International Workshop on Rapid Systems Prototyping (RSP 2003), pp. 179-185, San Diego, CA, (June 2003).
  86. P. Murphy; J. P. Frantz, E. Welsh; R. Hardy, T. Mohsenin, J. R. Cavallaro, “VALID: Custom ASIC Verification and FPGA Education Platform” Proc. 2003 IEEE International Conference on Microelectronic Systems Education, pp. 66-67, Anaheim, CA, (June 2003).
  87. J. R. Cavallaro, M. Vaya, “VITURBO: A Reconfigurable Architecture for Viterbi and Turbo Decoding,” Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), pp. 497-500, Volume II, Hong Kong, China (April 2003).
  88. M. L. Leuschen, I. D. Walker, J. R. Cavallaro, “Nonlinear Fault Detection for Hydraulics: Recent Advances in Fault Diagnosis and Fault Tolerance for Mechatronic Systems,” in Proc. 17th IEEE International Symposium on Intelligent Control, Vancouver, BC, Canada (October 2002).
  89. Y. Guo, J. R. Cavallaro, “Enhanced Power Efficiency of Mobile OFDM Radio using Predistortion and Post-Compensation,” Proc. IEEE 56th Vehicular Technology Conference, pp. 214-218, Vancouver, BC, Canada (September 2002).
  90. S. Rajagopal, S. Rixner, J. R. Cavallaro, “A Programmable Baseband Processor Design for Software Defined Radios”, IEEE Midwest Conference on Circuits and Systems, pp. 413-416, Tulsa, OK, (August 2002).
  91. Y. Guo, J. R. Cavallaro, “Post-Compensation Of RF Non-Linearity In Mobile OFDM Systems By Estimation Of Memory-Less Polynomial, Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 217-220, Volume I, Scottsdale, AZ (May 2002).
  92. F. Livingston, V. Chandrasekhar, M. Vaya, J. R. Cavallaro, “Handset Detector Architectures for DS-CDMA Wireless Systems”, Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 265-268, Volume III, Scottsdale, AZ (May 2002).
  93. Y. Guo, J. R. Cavallaro, “A Novel Adaptive Pre-Distorter Using LS Estimation Of SSPA Non-Linearity In Mobile OFDM Systems”, Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 453-456, Volume III, Scottsdale, AZ (May 2002).
  94. M. L. Leuschen, J. R. Cavallaro, I. D. Walker, “Robotic Fault Detection Using Nonlinear Analytical Redundancy”, Proc. IEEE International Conference on Robotics and Automation, pp. 456-463, Washington, DC (May 2002).
  95. Y. Guo, J. R. Cavallaro, “Reducing Peak-to-Average Power Ratio in OFDM Systems by Adaptive Dynamic Range Companding,” 3G Wireless, World Wireless Congress, paper 159, pp. 536-541, San Francisco, CA (May, 2002).
  96. Y. Guo, H. Zhang, X. Wang, Joseph R. Cavallaro, “VLSI Implementation of Mallat’s Fast Discrete Wavelet Transform Algorithm with Reduced Complexity,” IEEE Global Telecommunications Conference (Globecom), Volume 1, pp. 320-324, San Antonio, TX (November 2001).
  97. K. Chadha, J. R. Cavallaro, “A Reconfigurable Viterbi Decoder Architecture,” Proc. 35th Asilomar Conference on Signal, Systems, and Computers, Volume 1, pp. 66-71, Pacific Grove, CA (November 2001).
  98. S. Rajagopal, J. R. Cavallaro, “On-line Arithmetic for Detection in Digital Communication Receivers,” Proc. IEEE International Symposium on Computer Arithmetic, pp. 257-265, Vail, CO (June 2001).
  99. S. Rajagopal, J. R. Cavallaro, “A Bit-streaming Pipelined Multiuser Detector for Wireless Communications,” Proc. IEEE International Symposium on Circuits and Systems, Sydney, Australia, pp. 128-131, Volume IV, Sydney, Australia (May 2001).
  100. M. L. Leuschen, J. R. Cavallaro, I. D. Walker, “Testing on the Curve: Nonlinear Analytical Redundancy for Fault Detection,” Proc. Ninth ANS Topical Meeting on Robotics and Remote Systems, Session 22, Paper F131, Seattle, WA (March 2001).
  101. S. Das, E. Erkip, J. R. Cavallaro, B. Aazhang, “Maximum Weight Basis Decoding of Convolutional Codes,” Proc. IEEE Global Telecommunications Conference (Globecom), pp. 835-841, Volume 2, San Francisco, CA (November 2000).
  102. S. Rajagopal, B. A. Jones, J. R. Cavallaro, “Task Partitioning Wireless Base-station Receiver Algorithms on Multiple DSPs and FPGAs,” International Conference on Signal Processing Applications and Technology (ICSPAT), Dallas, TX, (October 2000) (Best paper award).
  103. M. L. Leuschen, I. D. Walker, J. R. Cavallaro, R. G. Gamache, M. Martin, “Experimental AR Fault Detection Methods for a Hydraulic Robot,” Proc. 18th International System Safety Conference, pp. 402-409, Fort Worth, TX (Sept. 2000).
  104. S. Rajagopal, S. Bhashyam, J. R. Cavallaro, B. Aazhang, “Efficient VLSI Architectures for Baseband Signal Processing in Wireless Base-Station Receivers,” IEEE 12th International Conference on Application-Specific Systems, Architectures and Processors (ASAP), pp. 173-184, Boston, MA (July 2000).
  105. B. Aazhang, and J. R. Cavallaro, “Multitier Wireless Systems,” Proc. Workshop On Strategic Research Plan for New Millennium Wireless World, Cagliari, Sardinia, Italy (May 2000).
  106. J. R. Cavallaro, “VLSI Architectures for Multi-tier Wireless Systems,” Proc Collaborative Technologies Workshop, Air Force Research Laboratory, Oakland University, pp. 28-31, Rochester, MI (November 1999).
  107. S. Das, S. Rajagopal, C. Sengupta, J. R. Cavallaro, “Arithmetic Acceleration Techniques for Wireless Communication Receivers,” 33rd IEEE Asilomar Conference on Signal, Systems, and Computers, pp. 1469-1474, Pacific Grove, CA (October 1999).
  108. V. Sundaramurthy, J. R. Cavallaro, “A Software Simulation Testbed for Third Generation CDMA Wireless Systems,” Proc. 33rd Asilomar Conference on Signal, Systems, and Computers, pp. 1680-1684, Pacific Grove, CA (October 1999).
  109. C. Sengupta, S. Das, J. R. Cavallaro, B. Aazhang, “Efficient Multiuser Receivers for CDMA Systems,” IEEE Wireless Communications and Networking Conference, pp. 1459-1463, New Orleans, LA (September 1999).
  110. G. Xu, J. R. Cavallaro, “Real-Time Implementation of the Multistage Algorithm for Next-Generation Wideband CDMA Systems,” Proc. SPIE Conference on Advanced Signal Processing Algorithms, Architectures, and Implementations IX, Volume 3807, pp. 62-73, Denver, CO (July 1999).
  111. D. Walker, J. R. Cavallaro, M. L. Leuschen, “Keeping the Analog Genie in the Bottle: A Case for Digital Robots,” IEEE International Conference on Robotics and Automation, pp.1063-1070,Detroit, MI (May 1999).
  112. M. L Leuschen, J. R. Cavallaro, I. D. Walker, “Monitoring and Diagnostics for a Hydraulic Robot in Hazardous Environments,” Proc. Eighth ANS Topical Meeting on Robotics and Remote Systems, Pittsburgh, PA (April 1999).
  113. S. Das, S. Bhashyam, J. R. Cavallaro, B. Aazhang, “Partially Blind Multiuser Detection,” Proc. Conference on Information Sciences and Systems, pp. 650-655, Baltimore, MD, (March 1999).
  114. C. Sengupta, S. Das, J. R. Cavallaro, B. Aazhang, “Joint Multiuser Channel Estimation and Detection for CDMA Systems,” Proc. IT Workshop on Detection, Estimation, Classification, and Imaging, Santa Fe, NM (February 1999).
  115. C. Carreras, I. D. Walker, O. Nieto, J. R. Cavallaro, “Robot Reliability Estimation using Interval Methods,” MISC’99 Workshop on Applications of Interval Analysis to Systems and Control, pp. 371-385, Girona, Spain (February 1999).
  116. M. Leuschen, I. D. Walker, J. R. Cavallaro, “Investigation of Reliability of Hydraulic Robots for Hazardous Environments using Analytic Redundancy,” IEEE Annual Reliability and Maintainability Symposium, pp. 122-128,Washington, DC (January 1999).
  117. S. Das, E. Erkip, J. R. Cavallaro, B. Aazhang, “Iterative Multiuser Detection and Decoding,” IEEE 7th Communication Theory Mini-Conference; in conjunction with Globecom, pp. 249-254, Sydney, Australia (November 1998).
  118. C. Sengupta, J. R. Cavallaro, B. Aazhang, “Maximum Likelihood Multipath Channel Parameter Estimation in CDMA Systems using Antenna Arrays,” Proc. 9th IEEE International Symposium on Personal, Indoor, and Mobile Radio Communications (PIMRC), CD-ROM Paper 398J017, Boston, MA (September 1998).
  119. S. Das, C. Sengupta, J. R. Cavallaro, “Hardware Design Issues for a Mobile Unit for Next Generation CDMA Systems,” Proc. SPIE Conference on Advanced Signal Processing: Algorithms, Architectures, and Implementations VIII, Volume 3461, pp. 476-487, San Diego CA (July 1998).
  120. C. Sengupta, S. Das, J. R. Cavallaro, B. Aazhang, “Fixed Point Error Analysis of Multiuser Detection and Synchronization Algorithms for CDMA Communication Systems,” Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing, Volume 6, pp. 3249-3252, Seattle, WA (April 1998).
  121. C. Sengupta, A. Hottinen, J. R. Cavallaro, B. Aazhang, “Maximum Likelihood Multipath Channel Parameter Estimation in CDMA Systems,” Proc. Conference on Information Sciences and Systems, Volume 1, pp. 6-11, Princeton, NJ (March 1998,).
  122. M. Leuschen, I. D. Walker, J. R. Cavallaro, “Robot Reliability Through Fuzzy Markov Models,” Proc. IEEE Annual Reliability and Maintainability Symposium, pp. 209-214, Anaheim, CA (January 1998).
  123. S. Das, J. R. Cavallaro, B. Aazhang, “Computationally Efficient Multiuser Detectors,” Proc. 8th IEEE International Symposium on Personal, Indoor, and Mobile Radio Communications (PIMRC), pp. 62-67, Helsinki, Finland (September 1997).
  124. C. Sengupta, J. R. Cavallaro, B. Aazhang, “Tracking Fading Multipath Channel Parameters in CDMA Systems using a Subspace Based Method – An Implementation Perspective,” Proc. 8th IEEE International Symposium on Personal, Indoor, and Mobile Radio Communications (PIMRC), pp. 734-739, Helsinki, Finland (September 1997).
  125. S. Das, J. R. Cavallaro, B. Aazhang, “Fast Multiuser Detector for a Time Varying CDMA System,” Proc. SPIE Conference on Advanced Signal Processing: Algorithms, Architectures, and Implementations VII, Volume 3162, pp. 569-580, San Diego, CA (July 1997).
  126. B. Haller, J. Götze, J. R. Cavallaro, “Efficient Implementation of Rotation Operations for High-Performance QRD-RLS Filtering,” Proc. IEEE International Conference on Application-specific Systems, Architectures, and Processors, (ASAP), pp. 162-174, Zurich, Switzerland (July 1997), Awarded Best Paper Award.
  127. J. R. Cavallaro, I. D. Walker, “Failure Mode Analysis of a Proposed Manipulator-based Hazardous Material Retrieval System,” Proc. American Nuclear Society 7th Topical Meeting on Robotics and Remote Systems, Vol. 2, pp. 1096-1102, Augusta, GA (April 1997).
  128. C. Sengupta, J. R. Cavallaro, B. Aazhang, “Solving the SVD Updating Problem for Subspace Tracking on a Fixed Sized Linear Array of Processors,” Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing, Volume 5, pp. 4137-4140, Munich, Germany (April 1997).
  129. B. M. Harpel, J. B. Dugan, I. D. Walker, J. R. Cavallaro, “Analysis of Robots for Hazardous Environments,” Proc. IEEE Annual Reliability and Maintainability Symposium, pp. 111-116, Philadelphia, PA (January 1997).
  130. M. L. Leuschen, I. D. Walker, J. R. Cavallaro, “Robot Reliability Using Fuzzy Fault Trees and Markov Models,” Proc. SPIE Conference on Sensor Fusion and Distributed Robotic Agents, Volume 2905, pp. 73-91, Boston, MA (November 1996).
  131. C. Sengupta, K. Kota, J. R. Cavallaro, “Parallel Algorithms and Architectures for Subspace-based Channel Estimation for CDMA Communication Systems,” Proc. SPIE Conference on Advanced Signal Processing Algorithms, Architectures, and Implementations VI, Volume 2846, pp. 412-423, Denver, CO (August 1996).
  132. D. L. Hamilton, J. R. Cavallaro, I. D. Walker, “Risk and Fault Tolerance for Robotics and Manufacturing,” Proc. 1996 IEEE Mediterranean Electrotechnical Conference, pp. 250-255, Bari, Italy (May 1996).
  133. B. Haller, B. Aazhang, J. R. Cavallaro, “Near-Far Resistant Code Synchronization for CDMA Systems – An Implementation Perspective,” Proc. 3rd International Conference on Telecommunications (ICT), Volume 1, pp. 441-448, Istanbul, Turkey (April 1996).
  134. M. Erdélyi, Zs. Bor, G. Szabó, J. R. Cavallaro, M. C. Smayling, F. K. Tittel, W. L. Wilson, Jr., “Sub-quarter Micron Contact Hole Fabrication Using Annular Illumination,” Proc. SPIE Conference on Optical Microlithography IX, Volume 2726, pp. 88-93, Santa Clara, CA (March 1996).
  135. C. Sengupta, M. Erdélyi, J. R. Cavallaro, M. C. Smayling, F. K. Tittel, W. L. Wilson, Jr., “An Integrated CAD Framework Linking VLSI Layout Editors and Process Simulators,” Proc. SPIE Conference on Optical Microlithography IX, Volume 2726, pp. 244-252, Santa Clara, CA (March 1996).
  136. D. Walker, J. R. Cavallaro, “The Use of Fault Trees for the Design of Robots for Hazardous Environments,” Proc. IEEE Annual Reliability and Maintainability Symposium, pp. 229-235, Las Vegas, NV (January 1996).
  137. J. R. Cavallaro, C. Sengupta, F. K. Tittel, W. L. Wilson, Jr., “Automated Evaluation of Critical Features in VLSI Layouts Based on Photolithographic Simulations,” Proc. of the NSF Design and Manufacturing Grantees Conference, SME Press, pp. 345-346, Albuquerque, NM (January 1996).
  138. J. R. Cavallaro, I. D. Walker, “Protective Operating System Shell Environment for Robots,” Proc. SPIE Sensor Fusion and Networked Robotics VIII, Volume 2589, pp. 194-205, Philadelphia, PA (October 1995).
  139. F. K. Tittel, M. Erdélyi, C. Sengupta, Zs. Bor, G. Szabó, J. R. Cavallaro, M. C. Smayling, W. L. Wilson, Jr., “Ultrahigh Resolution Lithography with Excimer Lasers,” NATO Workshop on Gas Lasers – Recent Developments and Future Prospects, Kluwer Academic Publishers, pp. 263-272, Moscow, Russia (July 1995).
  140. M. Erdélyi, C. Sengupta, Zs. Bor, J. R. Cavallaro, M. Kido, M. C. Smayling, F. K. Tittel, W. L. Wilson, Jr., G. Szabó, “A New Interferometric Shifting Technique for Sub-halfmicron Laser Microlithography,” Proc. SPIE Conference on Optical/Laser Microlithography VIII, Volume 2440, pp. 827-837, Santa Clara, CA (February 1995).
  141. Zs. Bor, J. R. Cavallaro, M. Erdelyi, M. Kido, C. Sengupta, M. C. Smayling, G. Szabó, F. K. Tittel, W. L. Wilson, Jr., “A New Phase Shifting Technique for Deep UV Excimer Laser Based Lithography,” Proc. SPIE Photonics West, Volume 2380, pp. 195-202, San Jose, CA (February 1995).
  142. J. R. Cavallaro, F. K. Tittel, W. L. Wilson, Jr., “Submicron Optical Microlithography Based on Interferometric Phase Shifting,” Proc. of the NSF Design, Manufacturing and Industrial Innovation Grantees Conference, SME Press, pp. 395-396, San Diego, CA (January 1995).
  143. F. K. Tittel, J. R. Cavallaro, M. Kido, M. C. Smayling, G. Szabó, W. L. Wilson, Jr., “Interferometric Phase Shift Technique for High Resolution Deep UV Microlithography,” Proc. SPIE Tenth International Symposium on Gas Flow and Chemical Lasers, Volume 2502, pp. 617-624, Friedrichshafen, Germany (September 1994).
  144. M. L. Visinsky, J. R. Cavallaro, I. D. Walker, “Adaptive Fault Detection and Tolerance for Robots,” Proc. First World Automation Conference, TSI Press, pp. 205-210, Wailea, HI (August 1994).
  145. K. Kota, J. R. Cavallaro, “Pipelining Multiple SVDs on a Single Processor Array,” Proc. SPIE Conference on Advanced Signal Processing Algorithms, Architectures, and Implementations V, Volume 2296, pp. 612-623, San Diego, CA (July 1994).
  146. N. D. Hemkumar, J. R. Cavallaro, “Jacobi-like Matrix Factorizations with CORDIC-based Inexact Diagonalizations,” Proc. Fifth SIAM Conference on Applied Linear Algebra, pp. 295-299, Snowbird, UT (June 1994).
  147. M. L. Visinsky, I. D. Walker, J. R. Cavallaro, “New Dynamic Model-Based Fault Detection Thresholds for Robot Manipulators,” Proc. IEEE International Conference on Robotics and Automation, pp. 1388-1395, San Diego, CA (May 1994).
  148. D. L. Hamilton, M. L. Visinsky, J. K. Bennett, J. R. Cavallaro, I. D. Walker, “Fault Tolerant Algorithms and Architectures for Robotics,” Proc. IEEE Mediterranean Electrotechnical Conference, pp. 1034-1036, Antalya, Turkey (April 1994).
  149. M. Kido, J. R. Cavallaro, W. L. Wilson, Jr., F. K. Tittel, “A New Phase Shifting Method for High Resolution Microlithography,” Proc. SPIE Conference on Optical/Laser Microlithography VII, Volume 2197, pp. 835-843, San Jose, CA (March 1994).
  150. J. R. Cavallaro, I. D. Walker, “A Survey of NASA and Military Standards on Fault Tolerance and Reliability Applied to Robotics,” Proc. AIAA/NASA Conference on Intelligent Robots in Field, Factory, Service, and Space (CIRFFSS’94), pp. 282-286, Houston, TX (March 1994).
  151. H. M. Fossati, F. K. Tittel, W. L. Wilson, J. R. Cavallaro, “Enhanced VLSI Manufacturability using an Integrated CAD Framework,” Proc. of the NSF Design and Manufacturing Grantees Conference, SME Press, pp. 549-550, Boston, MA (January 1994).
  152. M. Kido, J. R. Cavallaro, G. Szabó, W. L. Wilson, F. K. Tittel, “A New Phase Shifting Method for High Resolution Microlithography,” Proc. of the NSF Design and Manufacturing Grantees Conference, SME Press, pp. 577-578, Boston, MA (January 1994).
  153. M. L. Visinsky, J. R. Cavallaro, I. D. Walker, “Dynamic Sensor-Based Fault Detection for Robots,” Proc. SPIE Conference on Cooperative Intelligent Robotics in Space IV, Volume 2057, pp. 385-396, Boston, MA (September 1993).
  154. N. D. Hemkumar, J. R. Cavallaro, “Simulation of Systolic Arrays on the Connection Machine,” Proc. SCS International Simulation Technology Conference (SimTec), pp. 151-160, Clear Lake, TX (September 1993), (received Best Student Paper Award).
  155. K. Kota, J. R. Cavallaro, “CMOS Processor Element for a Fault-Tolerant SVD Array,” Proc. SPIE Conference on Advanced Signal Processing Algorithms, Architectures, and Implementations IV, Volume 2027, pp. 483-494, San Diego, CA (July 1993).
  156. N. D. Hemkumar, J. R. Cavallaro, “Efficient Complex Matrix Transformations with CORDIC,” Proc. IEEE 11th Symposium on Computer Arithmetic, pp. 122-129, Windsor, Ontario, Canada (June 1993).
  157. M. L. Visinsky, I. D. Walker, J. R. Cavallaro, “Layered Dynamic Fault Detection and Tolerance for Robots,” Proc. IEEE International Conference on Robotics and Automation, Volume 2, pp. 180-187, Atlanta, GA (May 1993).
  158. I. D. Walker, J. R. Cavallaro, “Parallel VLSI Architectures for Real-Time Kinematics of Redundant Robots,” Proc. IEEE International Conference on Robotics and Automation, Volume 1, pp. 870-877, Atlanta, GA (May 1993).
  159. I. D. Walker, J. R. Cavallaro, “Dynamic Fault Reconfigurable Intelligent Control Architectures for Robotics,” Proc. Fifth ANS Topical Meeting on Robotics and Remote Systems, pp. 305-311, Knoxville, TN (April 1993).
  160. M. L. Visinsky, J. R. Cavallaro, I. D. Walker, “Expert System Framework of Fault Detection and Fault Tolerance for Robots,” Proc. Fourth International Symposium on Robotics and Manufacturing, ASME Press Series on Robotics and Manufacturing, Volume 4, pp. 793-799, Sante Fe, NM (November 1992).
  161. K. Kota, J. R. Cavallaro, “A Normalization Scheme to Reduce Numerical Errors in Inverse Tangent Computations on a Fixed-Point CORDIC Processor,” Proc. IEEE International Symposium on Circuits and Systems, pp. 244-247, San Diego, CA (May 1992).
  162. N. D. Hemkumar, J. R. Cavallaro, “A Systolic VLSI Architecture for Complex SVD,” Proc. IEEE International Symposium on Circuits and Systems, pp. 1061-1064, San Diego, CA (May 1992).
  163. M. L. Visinsky, I. D. Walker, J. R. Cavallaro, “Fault Detection and Fault Tolerance in Robotics,” Proc. 1991 NASA Space Operations, Applications, and Research Symposium, pp. 262-271, Houston, TX (July 1991).
  164. N. D. Hemkumar, K. Kota, J. R. Cavallaro, “CAPE – VLSI Implementation of a Systolic Processor Array: Architecture, Design and Testing,” Proc. Ninth Biennial University/Government/Industry Microelectronics Symposium, IEEE Press, pp. 64-69, Melbourne, FL (June 1991).
  165. S. Deo, J. R. Cavallaro, I. D. Walker, “New Real-Time Robot Motion Algorithms using Parallel VLSI Architectures,” Proc. Fifth SIAM Conference on Parallel Processing for Scientific Computing, pp. 369-375, Houston, TX (March 1991).
  166. I. D. Walker, J. R. Cavallaro, “Parallel VLSI Architectures for Real-Time Control of Redundant Robots,” Proc. Fourth ANS Topical Meeting on Robotics and Remote Systems, pp. 299-309, Albuquerque, NM (February 1991).
  167. J. R. Cavallaro, A. C. Elster, “A CORDIC Processor Array for the SVD of a Complex Matrix,” Proc. 2nd International Workshop on SVD and Signal Processing, pp. 66-73, Kingston, RI (June 1990), and Proc. SVD and Signal Processing, II; Algorithms, Analysis and Applications, Elsevier Science Publishers B.V., pp. 227-239, (1991).
  168. J. R. Cavallaro, C. D. Near, M. Ãœ. Uyar, “Fault-Tolerant VLSI Processor Array for the SVD,” Proc. IEEE International Conference on Computer Design, pp. 176-180, Cambridge, MA (October 1989).
  169. J. R. Cavallaro, M. P. Keleher, R. H. Price, G. S. Thomas, “VLSI Implementation of a CORDIC SVD Processor,” Proc. Eighth Biennial University/Government/Industry Microelectronics Symposium, IEEE Press, pp. 256-260, Westborough, MA (June 1989).
  170. J. R. Cavallaro, F. T. Luk, “Floating-Point CORDIC for Matrix Computations,” Proc. IEEE International Conference on Computer Design, pp. 40-42, Rye Brook, NY (October 1988).
  171. J. R. Cavallaro, F. T. Luk, “CORDIC Arithmetic for an SVD Processor,” Proc. IEEE 8th Symposium on Computer Arithmetic, pp. 113-120, Como, Italy, (May 1987).
  172. J. R. Cavallaro, F. T. Luk, “Architectures for a CORDIC SVD Processor,” Proc. SPIE Real-Time Signal Processing IX, Volume 698, pp. 45-53, San Diego, CA (August 1986).
  173. D. J. Aneshansley, C. Pottle, J. R. Cavallaro, “Laboratory Workstations in Electrical Engineering,” Proc. IBM Academic Information Systems Advanced Education Projects (AEP) Conference, pp. 211-229, Alexandria, VA (June 1985).