Professor Cavallaro, in collaboration with Professor Behnaam Aazhang, is developing parallel architectures for code division multiple access (CDMA) wireless communication systems. This involves the use of parallel arrays of DSP/FPGA processors and custom VLSI processor architectures.

Current Projects

BRICK: Breaking the I/O and Computation Bottlenecks in Massive MIMO Base Stations

Massive multi-antenna (MIMO) wireless systems, in which the base-station is equipped with hundreds or thousands of antenna elements, will enable unprecedented data rates, cell coverage, and transmission reliability compared to that of existing cellular communication systems. The presence of hundreds or thousands of radio-frequency (RF) transceivers and antennas, however, results in excessively high internal data rates, which results in chip-interconnect and computation bottlenecks that prevent a straightforward deployment of this technology in practice. This project will develop new technologies that rely on decentralized signal processing at the base-station in order to avoid these bottlenecks, which leads to feasible and scalable solutions that enable base-station designs with thousands of antenna elements without sacrificing performance or reliability. In addition to enabling massive MIMO in practice, the project will advance future cellular networks through collaboration with the telecommunications industry, with the Argos massive MIMO testbed, and other network research testbeds. The project’s broader impact on education and outreach will include multiple components, including (i) training a diverse group of students as part of a collaborative, multi-institutional research team in the areas of communication theory and circuit design, (ii) integrating outcomes of the work into undergraduate and graduate courses, and (iii) making research outcomes broadly available through public-domain software packages and open-education resources via OpenStax courseware.

The project develops novel decentralized algorithms as well as very-large scale integration (VLSI) and general-purpose computing on graphics processing units (GPGPU) architectures based on antenna clustering and parallelization, for the uplink (users communicate to base-station) and the downlink (base-station communicates to users). The main idea of decentralized baseband processing is to divide the signal-processing workload at the base-station into multiple computing fabrics that are each connected to only a subset of RF transceivers and antennas. To reduce the chip-interconnect and computation bottlenecks the project investigates (i) optimization-based algorithms that exchange consensus information among the antenna clusters and (ii) message-passing-based algorithms that avoid such consensus exchange altogether. The most promising algorithm solutions will be implemented on field-programmable gate array and GPGPU clusters to assess the efficacy and limits of the developed solutions with real-world performance, hardware, and bandwidth constraints. The results of this analysis will provide guidelines that enable optimal massive MIMO base-station designs that use decentralized baseband processing.

Wireless LAN and MIMO FPGA Testbed

At Rice, the research focus is in new communication architectures that reconfigure based on the network availability, channel conditions and data rate requirements of a handset. The prototype architectures contain custom signal processing algorithms for the physical layer of wireless communication systems and are being implemented on Field Programmable Gate Array (FPGA) chips connected to high speed digital to analog (D/A) and analog to digital (A/D) converters. The digital baseband is then connected to custom RF radios in the 2.4 GHz ISM band. Realistic wireless channel conditions can be included through the use of real-time channel emulators in the Rice CMC Lab.

Furthermore, by designing algorithms with multiple transmit and receive antennae, we are developing new communications coding and feedback methods for high data rate wireless access. The new algorithms will be prototyped on the reconfigurable baseband platform, and stress tested in different wireless configurations for their robustness, performance limits and power efficiency. Initial stages in the prototyping of MIMO systems are underway.

The wireless research activities are continuing in the CMC lab with the new WARP testbed.

VLSI Signal Processing Research

The VLSI Signal Processing for Communications Group is presently involved in a number of projects to improve the real-time performance of parallel algorithms for wireless communication systems. The results of these projects are important for the development of the next generation of cellular mobile telephones. Support for this work has been provided by the National Science Foundation, the State of Texas, National Instruments, Texas Instruments, and Nokia Corporation.

Previous work in the group has been in the area of special-purpose architectures for matrix factorizations, including the Singular Value Decomposition (SVD). Computer arithmetic algorithms and their VLSI realizations, especially the CORDIC (Coordinate Rotation Digital Computer) algorithms, have been applied to the SVD. Applications of these architectures have included the inverse kinematics problem for the control of redundant robot manipulators.

Completed Projects

Gnomes Sensor Network Testbed

The Gnomes Sensor Network was composed of low-cost custom nodes designed and built at Rice University. Each node contains a Texas Instruments microcontroller, sensors and a wireless communications devices (typically Bluetooth). The Gnomes node has both battery and solar cells for power and can also be outfitted with a GPS receiver for position information. Low-power operation is one of the primary goals of Gnomes. Applications include remote monitoring of structures in collaboration with the Civil Engineering Department.